1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to how addresses of memory accesses are mapped to different regions of a memory.
2. Description of the Prior Art
It is known to provide data processing systems including a memory system. Such a memory system may have a plurality of different levels arranged in a hierarchy. As an example, a memory system may include a cache memory and a main memory. Within a single level within such a hierarchy there may be provided multiple different regions. As an example, a main memory may be split into a plurality of banks of bit cells. Each bank of bit cells may share the bit lines running therethrough. The bit lines are connected to a row of sense amplifiers supplying a buffer memory which may store one row of bit values at a time.
As process geometries fall in size, it becomes difficult to provide memories which have uniform properties in the multiple regions which may form such memories. The variations which arise may be the result of manufacturing variation, operating temperature or other reasons. Furthermore, the variations may change with time as different operating parameters change and also as the circuit ages. Variations may also arise independently of manufacturing differences, e.g. temperature differences.
One way of dealing with such variations within the behavioral characteristics of a memory is to operate the memory such that it assumes the worst case behavioral characteristics and yet still operates correctly. Whilst such an approach is safe, it reduces the maximum performance attainable in terms, for example, of speed, capacity, energy efficiency, mean time before failure etc.